EEPROM (Electrically Erasable Programmable Read Only Memory) cells are a class of nonvolatile semiconductor memory in which information may be electrically programmed into and erased from each memory element or cell. Floating gate EEPROM cells are one type of EEPROM cell in which information is stored by placing electronic charge on a “floating gate,” typically a region of conductive polysilicon that is electrically isolated from other conducting regions of the device by insulating dielectric layers that surround it. The charge on the floating gate can be detected when reading the memory cell because the charge changes the threshold voltage of the memory transistor. This change in threshold voltage varies the amount of current that flows through the cell when voltages are applied to the cell during the read operation and the current can be detected by a sense amplifier circuit.
One technique often used in advanced process to create EEPROM devices having gate and junction regions with reduced resistivities is a salicide process. The salicide process uses a layer of self-aligned silicide (“salicide”), which reduces the resistivity of the gate and junction regions of a device. A silicide layer is obtained by depositing titanium, or another transition metal, on the entire surface of the device, and applying a heat treatment that causes the titanium to react with the underlying silicon in the gate and junction regions to form a titanium silicide layer. Subsequently, the non-reacted titanium deposited on the oxide regions is removed by etching with an appropriate solution, which leaves the titanium silicide intact. Traditionally, the salicide process has been used for fabricating low voltage CMOS devices having gate widths below approximately 0.35 microns.
As geometries of the devices continue to shrink, developing an integrated process to combine low-voltage devices with high-voltage devices and non-volatile memory devices, such as EEPROMs, becomes more challenging. A conventional salicide process is typically incompatible with requirements for high-voltage devices that have shallow, lightly doped source/drain junctions because it is difficult to develop a reliable integrated fabrication process flow that combines low-voltage, high-voltage and non-volatile memory devices together in one process. The lightly doped junctions require a balance between low junction leakage and high breakdown voltage. Low junction leakage typically implies a high doping concentration, while high breakdown voltage implies a low doping concentration. Additionally, there is a tradeoff between low sheet resistance (e.g., thick salicide) and low silicon consumption for shallow junctions (e.g., thin salicide), and scaling the salicide thickness to reduce the junction leakage is typically not an option.
Due to the tradeoffs between junction leakage and high breakdown voltage, prior art solutions have not used the salicide process for devices having shallow, lightly doped junctions with high-voltage requirements. In one prior art solution, a process for fabricating a flash EEPROM involves saliciding low-voltage logic, memory cells and the source and drain regions of high-voltage devices. The fabrication process, however, does not use a salicide process to form the gate region of the high-voltage device. In another prior art solution, an EEPROM process flow salicides low-voltage devices, the source and gate regions of memory cells and the gate region of the high-voltage devices. The process flow, however, avoids saliciding the source and drain regions of the high-voltage devices and the drain diffusion regions of the memory cells since each junction is lightly doped. A further prior art solution salicides entire regions of memory and low-voltage devices. However, this solution provides no technique for saliciding high-voltage devices.
While the described prior art solutions employing a salicide process for fabrication of low-voltage, high-voltage and non-volatile memory devices are an improvement over earlier solutions, they still have several drawbacks. Accordingly, a technique to simultaneously fabricate low-voltage, high-voltage and memory devices is desired.